1. Field of the Invention
This invention relates to a digital signal process (DSP) for processing various digital signals depending upon any programs.
2. Description of the Prior Art
Nowadays several digital signal processing algorithms are implemented with a hardwired device or a programmable DSP. Such digital signal processing algorithms include complex arithmetic formulas such as fast fourier transform (FFT). For example, "AC-3" suggested as an audio compression and reconstruction algorithm by Dolby Co. Ltd. uses IFFT having a block length of "64" when being intended to improve a resolution of a signal on the time axis; while it uses IFFT having a block length of "128" when being intended to improve a resolution of a signal on the frequency axis. As shown in FIG. 1, such a reverse transform method of the AC-3 algorithm includes a pre-IFFT, a complex IFFT and a post-IFFT that are successively performed after coefficients to be used in the transform are defined. Also, a windowing arithmetic and an overlap and add arithmetic followed by the post-IFFT are sequentially performed. FIG. 2 shows an embodiment of a radix-2 FET algorithm having a block length of "8". In the radix-2 algorithm, a butterfly structure arithmetic as shown in FIG. 3 is used regularly. The butterfly structure arithmetic as shown in FIG. 3 can be expressed as the following equations: EQU X.sub.out =x.sub.in +y.sub.in.multidot.W.sup.k.sub.N EQU Y.sub.out =x.sub.in -y.sub.in.multidot.W.sup.k.sub.N. (W.sup.k.sub.N =e.sup.-2.pi.k/N) EQU Re(X.sub.out)=Re(x.sub.in)+Re(y.sub.in)cos(-2.pi.k/N)-Im(y.sub. in)sin(-2.pi.k/N) EQU Im(X.sub.out)=Im(x.sub.in)+Im(y.sub.in)cos(-2.pi.k/N)+Re(y.sub. in)sin(-2.pi.k/N) EQU Re(Y.sub.out)=Re(x.sub.in)-Re(y.sub.in)cos(-2.pi.k/N)+Im(y.sub. in)sin(-2.pi.k/N) EQU Im(Y.sub.out)=Im(x.sub.in)-Im(y.sub.in)cos(-2.pi.k/N)-Re(y.sub. in)sin(-2.pi.k/N) (1)
wherein Re(x) and Im(x) represent a real number part and an imaginary number part, respectively. Also, in the radix-2 algorithm of FIG. 2, butterfly arithmetical groups are multiplexed. The butterfly arithmetical group is obtained by multiplexing the butterfly structure arithmetics, as shown FIG. 4. Further, the radix-2 algorithm with the multiplexed butterfly arithmetical groups is provided to the FFT, as a butterfly arithmetical stage. Accordingly, the FFT consists of the plurality of the butterfly arithmetical stages. In order to operate the FFT, conventional DSPs repeatedly perform steps as shown in the flowchart of FIG. 5.
In order to perform all the operations which are from the simple four arithmetical operations to the FFT including the butterfly structure operation, in the DSP, how fast can each command word be processed is regarded as an important factor. In other words, a period of the command word in the DSP must be shortened and command words as much as possible must be processed in parallel so as to perform a high speed process of the command word. The command word parallel processing capability has required from the time when the DSP was used for the video/audio decoder, and which can be attained by carrying out a plurality of commands in parallel differently from the previous sequential command execution. Accordingly, the recent DSPs has been provided with special command words permitting the parallel process. For example, the ADSP in ADSP21020 model of Analog Device Co. has special command words that allow a number of complex arithmetic equations to be processed within only several clock periods like the butterfly operation for the FET arithmetic. To this end, the ADS21020 is provided with a register file consisting of at least 12 registers related to the operation. Further, the DSP in ZR38000 model of Zoran Co. can process a number of complex arithmetic equations within several clock periods. To this end, the ZR38000 has a register file consisting of 8 registers and a structure which is capable of performing a multiplication and a resultant addition and subtraction at a time within one clock period.